RT-LAB | RT-XSG

Key Features

Allows for FPGA target code to be included as part of a larger real-time simulation model.
Handles the model C code generation via Real Time Workshop (RTW) and the FPGA HDL code generation via XSG transparently.
Loads the generated bitstream on the hardware during the loading of the real-time model.
The RT-XSG is a system level modeling tool that facilitates FPGA hardware design for those that are not FPGA experts. Xilinx System Generator is an add-on to Simulink developed by Xilinx.

RT-XSG can be used in standalone mode in order to provide configuration data when operating in the MATLAB/Simulink environment. It can also be used when modeling within the RT-LAB® environment, providing the user with a state-of-the-art solution for advanced FPGA-accelerated Real-Time and HIL system simulation.

RT-XSG provides a convenient, Simulink-based way to build models. Using the RT-XSG toolbox saves time when conducting FPGA-based co-simulation, since it automatically manages configuration file generation on each supported platform. It also manages the configuration of the platform, along with the transfer of high-bandwidth data between RT-LAB simulation models and the user-defined custom model, built using RT-XSG, and executed on an FPGA device.

While conventional processor designs operate sequentially on a set of instructions, FPGA processors perform operations in parallel. This makes them ideally suited for very fast simulation of loosely-coupled models. Some examples of applications already implemented using RT-XSG are:

High-speed digital and/or analog waveform generators
Signal processing, windowing and analysis
Embedded simulation of stiff (high-speed dynamics) models, such as electrical motor models

RT-XSG allows for FPGA target code to be included as part of a larger real-time simulation model. The model includes all parts of the simulation while C code and FPGA HDL code are automatically generated and dispatched by RT-XSG. It enables the creation FPGA HDL without knowledge of the language.

RT-XSG already provides FPGA-specific blocks which include the standard functionalities of Opal-RT's FPGA-based cards:

Full integration with Simulink and RTW
Static digital inputs and outputs
Interface to fast OP5000 DAC and ADC modules


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RT-XSG Key Features Allows for FPGA target code to be included as part of a larger real-time simulation model. Handles the model C code generation via Real Time Workshop (RTW) and the FPGA HDL code generation via XSG transparently. Loads the generated bitstream on the hardware during the loading of the real-time model. The RT-XSG is a system level modeling tool that facilitates FPGA hardware design for those that are not FPGA experts. Xilinx System Generator is an add-on to Simulink developed by Xilinx. RT-XSG can be used in standalone mode in order to provide configuration data when operating in the MATLAB/Simulink environment. It can also be used when modeling within the RT-LAB® environment, providing the user with a state-of-the-art solution for advanced FPGA-accelerated Real-Time and HIL system simulation. RT-XSG provides a convenient, Simulink-based way to build models. Using the RT-XSG toolbox saves time when conducting FPGA-based co-simulation, since it automatically manages configuration file generation on each supported platform. It also manages the configuration of the platform, along with the transfer of high-bandwidth data between RT-LAB simulation models and the user-defined custom model, built using RT-XSG, and executed on an FPGA device. While conventional processor designs operate sequentially on a set of instructions, FPGA processors perform operations in parallel. This makes them ideally suited for very fast simulation of loosely-coupled models. Some examples of applications already implemented using RT-XSG are: High-speed digital and/or analog waveform generators Signal processing, windowing and analysis Embedded simulation of stiff (high-speed dynamics) models, such as electrical motor models RT-XSG allows for FPGA target code to be included as part of a larger real-time simulation model. The model includes all parts of the simulation while C code and FPGA HDL code are automatically generated and dispatched by RT-XSG. It enables the creation FPGA HDL without knowledge of the language. RT-XSG already provides FPGA-specific blocks which include the standard functionalities of Opal-RT's FPGA-based cards: Full integration with Simulink and RTW Static digital inputs and outputs Interface to fast OP5000 DAC and ADC modules

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