Simon Abourida
Publication date : Feb 2008
Paper File :
2008_ICAS-AbouridaS-HIL for Aeronautic systems.pdf
Authors
Simon Abourida, Abstract
Avionics, navigation systems, flight controls and power units are becoming increasingly sophisticated within aerospace and defense systems (airplanes, UAVs, missiles…).
Hardware-in-the-loop simulation is a cost-effective method for testing the complex, flight critical hardware before it is used in the real world. This paper discusses Real-Time and Hardware-In-The Loop simulation used for the design and testing of these systems. The paper describes the general design and architecture of an advanced real-time, distributed processing, PC- and FPGA-based simulator platform (RT-LAB), and gives several examples of the uses and applications of this platform for the design, tuning and testing of aeronautic systems.
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Publication date : Jan 2010
Paper File :
2009_icmsao_RTsim_v2.pdf
Authors
Simon Abourida, Jean Bélanger, Abstract
The paper presents state-of-the-art technologies and platform for real-time simulation and control of motor drives, power converters and power systems.
Through its support for Model-Based Design method with Simulink®, its powerful hardware (multi-core processors and FPGAs), and its specialized model libraries and solvers, this realtime simulator (RT-LAB™) enables the engineer and researcher to efficiently implement advanced control strategies on embedded hardware, or to conduct extensive testing of complex power electronics and real-time transient simulation of large power systems.
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eDRIVEsim Electric Motors, Drives, and Power Electronics High Fidelity Hardware in the Loop (HIL) and ECU Testing_en
Publication date : Sep 2008
Paper File :
Paper_ISIE08.pdf
Authors
Vincent Lapointe, Simon Abourida, Jean Bélanger, Christian Dufour, Abstract
Presented in this paper are the results of closed-loop control experiments using a virtual permanent magnet synchronous motor (PMSM) drive implemented on a fieldprogrammable gate array (FPGA) card connected to an external controller. The FPGA-based PMSM motor drive is implemented on an eDRIVEsim simulator, based on the RT-LAB platform. The eDRIVEsim simulator implements 2 types of motor drive models, Park (d-q) and Finite Element Analysis (FEA), on an FPGA card of the simulator.
The FPGA-based motor model is designed with Xilinx System Generator (XSG) blockset with no HDL hand coding. Both motor models compute motor currents using a phase-domain algorithm solver that can take into account the instantaneous variation of
inductance and non-sinusoidal induced voltage. The FEA-type model uses inductance and Back-EMF profiles computed with JMAG-RT. The d-q model uses sinusoidal induced Back-EMF voltage and phase inductance values computed from Ld and Lq using the well-known Park transformation. A 3-phase IGBT inverter implemented in the FPGA chip drives the PMSM machine.
The PWM controller is designed using Rapid Control Prototyping (RCP) methodology based on Simulink. It is implemented on an separate RT-LAB system using standard Opal-RT FPGA-based I/O cards for Analog Input capture and PWM generation. The paper presents results from the closed-loop control of the PMSM drive in both current control and speed control modes and discusses the advantages of using such a virtual test bench for motor drives.
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eDRIVEsim Electric Motors, Drives, and Power Electronics High Fidelity Hardware in the Loop (HIL) and ECU Testing_eneDRIVEsim - Simulateur Temps Réel pour les Moteurs et Systèmes Électriques_fr
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